Need help debugging my schematic

I’m working on a small atmega168 breakout board and I’m having to dig up my cob-webby EE knowledge to design the schematic. In version 1.0 of the board, I think I made a critical error, and could use a hand in figuring out how to correct/work-around a potential issue.

Summary: An atmega chip needs the reset line to remain HIGH to stay out of RESET and run code. What I did was as follows in the attached image… I connected a 100nF capacitor to the RESET line, then ran that through a 1K resistor to VCC to keep the voltage high. The resistor is also connected to an open jumper ( I just used a 0 ohm resistor part, then didn’t populate it to leave it blank ) that goes to GND.

In theory, this means that the capacitor will charge up to VCC, then hold at VCC for as long as it’s connected through the resistor – however if GND gets connected it will drain charge and drop to GND ( 0V in theory ) and reset the chip.

In practice, this does not seem to work as I expect it to. I know that in DC circuits, capacitors when charged do not pass current – but in this case I thought that it would hold the voltage at VCC… just like a battery would and thus hold the RESET line high.

The pink line represents the trace on the back side of the board, connecting the vias. The four vias are isolated from the ground plane. Only the fifth via ( up near GND marking ) is connected fully to the ground plane ( as are the GND pins on the chip ).

When a cap is charged, there’s a voltage differential between the pins. I don’t know anything about the atmega specifically, but in this circuit I’d expect the pin on U1 to be high or low according to the internal pull configuration. If it’s high-Z then weirdness would happen that my analog-fu isn’t strong enough to guess at.

I think what you wanted to do is put the cap between reset and ground, then pull up the reset line via R2. Then reset will start low, then transition high as the cap charges.

Sounds reasonable … here’s my “v1.1” take on it